Documenting an undocumented chip: the TensorCore of TPU v5e — Gherkin Labs

Researchers at Gherkin Labs have documented the unofficial instruction set and architecture of the TensorCore in Google's TPU v5e chip. Using an in-house assembler, a minimal driver, and LLM-guided exploration probes, the authors mapped out pipeline execution, vector ALU operations, memory layouts, and instruction latencies. Open article →