Qualcomm Validates HBC Stacked Memory Ahead of 2027 Dragonfly AI250 Sampling

Qualcomm has completed initial validation of its High Bandwidth Compute stacked memory architecture, which places DRAM dies directly on top of a compute die. Testing of an early two-layer sample showed five times the bandwidth-per-watt efficiency of HBM4. The technology is scheduled to begin commercial sampling in the Dragonfly AI250 accelerator next year. Open article →