Engineer overclocks Specula RISC-V core to 99 MHz

An engineer details the process of optimizing an out-of-order RISC-V processor core named Specula from 12 MHz to roughly 99 MHz on an FPGA. Through iterative refactoring—such as replacing a combinational divider, restructuring comparison trees, splitting memory pipeline stages, and eliminating redundant bypasses—the author navigated synthesis tool noise and area constraints to meet practical timing targets. Open article →