divagr1925/QwenPU: A 32-bit RISC-V CPU and vector unit compiled into Qwen weights

QwenPU is a modified Qwen3.5-4B model featuring a compiled 32-bit RISC-V CPU and vector unit within its weights, enabling it to execute a neural network program during its forward passes. The system successfully runs Andrej Karpathy's stories260K program with zero mismatches against a reference model, producing token-by-token exact story generation. The current 26.7 GB checkpoint requires a GPU with 40 GB or more of memory to load entirely, though trimming the hidden size is planned. Open article →