Student builds Specula out-of-order RV32I core on Artix-7 FPGA

An engineering student built Specula, a single-issue out-of-order RISC-V processor written in Bluespec SystemVerilog, designed to boot the xv6 operating system and target an Artix-7 FPGA. Through iterative optimizations including replacing a combinational divider with an iterative radix-2 design, restructuring memory queues, and downsizing the reorder buffer, the design successfully fits within the FPGA's resource constraints. Open article →